1. Field
The various method and circuit embodiments described herein relate in general to low-drop out (LDO) regulators, and, more specifically, to self-calibrating, stable LDO regulators of the type described that are substantially unconditionally stable and which can be constructed with small or no capacitor structures.
2. Background
LDO regulators are linear DC voltage regulators, and are used widely in mixed-signal system on chip (SoC) devices. Present-day SoCs, for example, may contain digital, analog, mixed-signal, and often radio-frequency functions, all on a single chip or substrate, which may, for instance, form a part of an embedded system. Examples of some of the various circuits that may be found on an SoC may include amplifiers, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), phase-locked loops (PLLs), and the like.
Many of the mixed signal SoC functions produce spurious emissions in the Megahertz range of frequencies, where traditional LDO regulators do not maintain low-impedance output. This negatively impacts the isolation between the various circuits on the SoC. Nevertheless, LDO regulators often are used for supply isolation between various SoC circuits.
An electrical schematic diagram of a typical LDO regulator 10 is shown in FIG. 1, to which reference is now made. The LDO regulator 10 has a first amplifier 12 having a reference voltage (VBG) on its non-inverting input, provided, for example, by a band-gap reference voltage supply (not shown). VBG may be, for instance, about 1.0 V or 1.2 V. The inverting input of the first amplifier 12 has a fraction of the output voltage applied thereto that is developed by a resistor divider that includes resistors 14 and 16. The voltage applied to the inverting input of the first amplifier 12 may be about equal to VBG, so that the voltage output of the first amplifier 12 represents the voltage difference between VBG and the divided voltage developed at the tap on resistor 16. The first amplifier 12 may have a relatively low bandwidth, for example, of about 10 KHz to limit the noise from the band-gap voltage regulator that may otherwise pass to the output.
A second amplifier 18 receives the output from the first amplifier 12. The second amplifier 18 has a wide bandwidth, for example, of about 1 MHz, to maintain a low-impedance output across its operating frequencies, up to a known corner frequency. The output of the second amplifier 18 is connected to the gate of an FET 20. The source of the FET 20 is connected to VCC and the drain is connected to one end of the resistor 16. The other end of the resistor 16 is connected to a reference potential, or ground. The output of the LDO regulator is taken from the drain of the FET 20 on node 22, and is typically about 1.4 V.
LDO regulators of the type shown in FIG. 1 typically have two loops, one having a high impedance node 19 at the gate of the FET 20, driving a single low impedance output, Vout, on node 22. The output impedance, therefore, is established by the total resistance of the resistors 14 and 16 divided by the loop gain. Such LDO regulators are best suited for off-chip capacitor structures or in applications where the bandgap voltage, VBG, is far away from the LDO regulator output voltage, VOUT. Traditional LDO regulators are designed for given load currents and capacitances, and have to be stable for a given ILOAD/CLOAD. However, the stability of traditional LDO regulators degrades dramatically under low load current and high load capacitance scenarios. Moreover, traditional LDO regulators have poor suppression of spurious emissions at high frequencies.
As shown in the graph of FIG. 2, traditional LDO regulators of the type shown in FIG. 1 maintain a low R in the OUT 20 ohm range below about 1 MHz, illustrated by the curve 24. This gradually increases into the Kohm range at higher frequencies, shown by the curve 26. At frequencies above 10 MHz, Rout may be greater than 200 ohms, and may increase to the Mohm range at even higher frequencies. At the same time, the bandwidth of the second amplifier 18 circuit is substantially flat up to 1 MHz, shown by curve 28, then decreases above 1 MHz, shown by curve 30.
The efficiency of the circuit 10, Rout—eff, is approximately Rout/(loop gain). Rout is established by the size of the resistors 14 and 16, which may be on the order of about 100 Kohms. However, as the loop gain starts to fall above a 3 dB frequency, Rout starts to go up (see, for example, the curves of FIG. 2 where the 3 dB frequency is about 1 MHz). Consequently, in the past, LDO regulators had to be redesigned every time with each new application, depending on the frequencies of operation and the capacitive loads on the output.
In addition to the challenges described above, present LDO regulators require a large portion of the circuit area in integrated circuit constructions. For example, in a PLL, an LDO regulator may take as much as ¼ of the PLL area.
The current consumption and necessary decoupling capacitors vary greatly from application to application. Analog circuits are mostly designed with VDDA (˜=1.4V) using high voltage gate devices. Digital circuits require VDD regulation to 1.2V, as they are built using core devices. Currents of most analog blocks are small, for example, about 2 to 5 mA. However, most analog blocks are sensitive to SoC noise. For example, in mixed signal applications, ADC, DAC, and PLL circuits generate noise at their clock frequencies, which may be between about 1 to 50 MHz. As discussed above, traditional LDO regulators have a very large ROUT at the higher range of these frequencies. Consequently, LDO regulators are often designed to be independent of the analog block currents and noise.
What is needed, therefore, is an unconditionally stable LDO regulator to drive loads over a large range of load capacitors and currents. There is also a need for a small LDO regulator that has a low output resistance, ROUT, at MHz frequencies, and that can supply current to both analog and digital circuits.